GPU-accelerated tools for RTL optimization and physical design.
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Partcl
Overview
Partcl modernizes chip design automation with physics-informed models powered by GPU acceleration.
Our tools run up to 700× faster than legacy solutions, cutting weeks off development and unlocking AI-driven optimization.
Product details
Founders & team
Previously AionCAD
William Salcedo
Founder/CEOCEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.
Vamshi Balanaga
Founder/CTOCTO at Partcl. Previously built embedded ML models at Apple, laser weeding robots at Carbon Robotics, and warehouse automation robots at Fulfil Solutions. Built and launched multiple rockets while running the avionics team at Space Enterprise at Berkeley, Stanford EECS PhD (dropout), UC Berkeley Physics.
Founded 2025 · Source
News & product activity
Sources & observations
Maturity: Not assessed · 3 of 6 areas documented
Source-based assessment · automated evidence rules
The retained text does not establish product availability or customer use.
Maturity is an evidence-based assessment, not a success rating. It may understate the current stage where evidence is limited. Coverage records documented areas, not a complete or independently audited company history.
- Product overviewSource description Checked 2026-11-11
- Product visualsNot documented
- Founders & originsTeam information
- Business model & pricingNot documented
- Funding & ownershipNot documented
- Dated milestonesDated source activity: 2025 Q2 (quarter only)





